# TSMC’s January 2026 call confirmed N2 high-volume manufacturing had begun in 4Q25 TSMC said on January 15, 2026 that N2 had entered high-volume manufacturing in 4Q25, distinguishing its first nanosheet-node ramp from later variants. Canonical: https://rangoon.ai/insights/archive-tsmc-n2-high-volume-manufacturing-january-2026/ Author: Rangoon Editorial (https://rangoon.ai/insights/editorial/) Published: 2026-10-23 Updated: 2026-10-23 Event date: 2026-01-15 Tags: [TSMC](https://rangoon.ai/insights/tags/tsmc/), [N2](https://rangoon.ai/insights/tags/n2/), [2nm](https://rangoon.ai/insights/tags/2nm/), [nanosheet transistors](https://rangoon.ai/insights/tags/nanosheet-transistors/) Source note: Historical reporting: TSMC’s January 15, 2026 earnings-call transcript said N2 had entered high-volume manufacturing in 4Q25 with good yield. The public 2nm technology page provides later maintained process context. This article does not assign an unverified December start day, identify customer products, or treat TSMC’s process-performance projections and yield characterization as independent measurements. Image: N2 ramp from transistor process to packaged system. Original Rangoon explanatory diagram: Source boundary: dated primary release reporting; original editorial analysis. Not measured results, official guidance, vendor interface, or event photograph. ## Key takeaways - TSMC publicly confirmed in January that N2 entered high-volume manufacturing during 4Q25; the record does not name a specific December day. - N2 introduced TSMC’s first-generation nanosheet transistor technology, while N2P and A16 remain separate later variants. - High-volume manufacturing and good yield do not reveal customer mix, wafer output, product availability, or end-system performance. ## The dated confirmation named a quarter, not an invented December start date [source 1](https://investor.tsmc.com/schinese/encrypt/files/encrypt_file/reports/2026-01/51d09df96cd89ac19d65af39032b038dc2896a24/TSMC%204Q25%20Transcript.pdf) At its January 15, 2026 earnings call, TSMC said N2 had successfully entered high-volume manufacturing in the fourth quarter of 2025 at Hsinchu and Kaohsiung, with good yield. That is a public confirmation of a 4Q25 manufacturing milestone. It does not identify the exact calendar day in December, a particular wafer count, or a customer product that had reached market. The distinction matters because announcements, risk production, high-volume manufacturing, wafer revenue, packaged-device availability, and finished-system shipment are separate milestones. A timeline should preserve the quarter TSMC actually stated rather than turning it into a more precise date than the source provides. ## N2 changed the transistor architecture while retaining a process-family boundary [source 1](https://investor.tsmc.com/schinese/encrypt/files/encrypt_file/reports/2026-01/51d09df96cd89ac19d65af39032b038dc2896a24/TSMC%204Q25%20Transcript.pdf) [source 2](https://www.tsmc.com/english/dedicatedFoundry/technology/logic/l_2nm) TSMC’s current 2nm page describes N2 as its first-generation nanosheet transistor technology and says it started volume production in 4Q25 as planned. A nanosheet device changes the gate’s relation to the channel compared with a FinFET, giving a foundry another set of geometry and electrostatic tradeoffs. That process description is maintained context, not evidence that a particular customer design or library was ready on the call date. The same public materials distinguish N2 from N2P and A16, which TSMC schedules separately. Treating every label in an N2 family as one launch would erase differences in process options, design rules, power delivery, and production timing. ## A high-volume ramp still has yield, design and packaging dependencies [source 1](https://investor.tsmc.com/schinese/encrypt/files/encrypt_file/reports/2026-01/51d09df96cd89ac19d65af39032b038dc2896a24/TSMC%204Q25%20Transcript.pdf) [source 2](https://www.tsmc.com/english/dedicatedFoundry/technology/logic/l_2nm) A leading-edge ramp has to control defect density, transistor variation, interconnect resistance, SRAM behavior, process windows, and design-rule compliance at a scale that supports repeated manufacturing. Good yield in a company statement is directional process information, not a disclosed yield distribution across all products. A chip designer also has to complete physical implementation, signoff, mask preparation, wafer processing, test, packaging, and its own qualification sequence. For AI hardware, advanced packaging and memory integration can add another schedule beyond logic-wafer availability. A successful node ramp therefore does not automatically make a complete accelerator, server, or cluster available. ## Node projections must stay separate from delivered product performance [source 1](https://investor.tsmc.com/schinese/encrypt/files/encrypt_file/reports/2026-01/51d09df96cd89ac19d65af39032b038dc2896a24/TSMC%204Q25%20Transcript.pdf) [source 2](https://www.tsmc.com/english/dedicatedFoundry/technology/logic/l_2nm) TSMC’s technology page presents process-level performance, power, and density projections relative to an earlier node under stated comparison conditions. Such figures help describe a foundry target, but they do not predict the behavior of every CPU, GPU, accelerator, or mobile system built on the process. Circuit mix, SRAM, analog blocks, voltage targets, library choices, packaging, and software workload can each change the visible result. The January event supports a narrow historical conclusion: N2 reached the high-volume-manufacturing stage in 4Q25 according to TSMC. It does not establish who used it first, what product shipped first, or an independent advantage over a competing process. ## Sources 1. [TSMC: 4Q 2025 earnings-call transcript](https://investor.tsmc.com/schinese/encrypt/files/encrypt_file/reports/2026-01/51d09df96cd89ac19d65af39032b038dc2896a24/TSMC%204Q25%20Transcript.pdf) 2. [TSMC: 2nm Technology](https://www.tsmc.com/english/dedicatedFoundry/technology/logic/l_2nm) ## Related reading - [TSMC’s Arizona expansion announcement separated a $100 billion plan from current fab output](https://rangoon.ai/insights/archive-tsmc-arizona-investment-march-2025/) - [TSMC’s A14 statement kept a 2025 unveiling separate from a 2028 plan](https://rangoon.ai/insights/archive-tsmc-a14-roadmap-statement-2025/) - [TSMC’s 2025 CoWoS disclosure framed packaging as a planned capacity constraint](https://rangoon.ai/insights/archive-tsmc-cowos-capacity-planning-2025/) ## More information - [Documentation index](https://rangoon.ai/llms.txt) - [AI access and policies](https://rangoon.ai/ai/) - [Source repository](https://github.com/hypler-dev/rangoon)