TSMC’s 2025 CoWoS disclosure framed packaging as a planned capacity constraint

What TSMC disclosed^{[source 1][source 2]}

In its 2024 annual-report publication dated April 17, 2025, TSMC said it was developing advanced packaging and 3D chip-stacking technologies including CoWoS, InFO, and SoIC, and working with customers to plan capacity for structural demand. The disclosure identifies packaging as a manufacturing investment area rather than an invisible afterthought to logic fabrication.

TSMC’s 2025 annual-report material describes CoWoS as integrating multiple system-on-chip dies and high-bandwidth-memory stacks to enhance HPC products. That explains the technology’s role. It does not provide a universal package lead time, an allocation for a particular customer, or proof that every planned capacity expansion had already produced shippable packages.

Editorial analysis: capacity has several denominators

A capacity number can mean cleanroom space, installed equipment, qualified line capacity, theoretical throughput, tested throughput, customer allocation, or finished-good output. These are different denominators. A package line also depends on substrates, interposers, HBM availability, assembly, test, and thermal materials, so one bottleneck can limit the whole result.

Planning records should name the denominator, period, technology mix, yield assumption, and supply dependencies. If a company reports investment or expansion intent, preserve it as a plan. If it reports qualified output, identify the product class and measurement period. This avoids converting capital expenditure into immediate package supply.

Editorial analysis: package integration is a product gate

CoWoS connects logic and memory in a package whose behavior must be evaluated as an assembly. Validation can include interconnect integrity, HBM behavior, thermal cycling, warpage, power delivery, test coverage, and workload performance. A good logic die and a good HBM stack do not guarantee a qualified package without this integration evidence.

A package readiness record should link die revisions, HBM revision, interposer, substrate, assembly flow, test program, thermal solution, and target workload. It should distinguish engineering lots from qualified product lots. This makes the status useful to system teams that must plan servers, boards, and deployments.

Editorial analysis: pair demand plans with evidence

Advanced-packaging demand can rise faster than a planner expects because it is tied to accelerator and HBM configurations rather than logic wafers alone. Forecasts should therefore include scenario ranges, customer commitments where available, supplier lead times, and an explicit uncertainty state. A requested package is not capacity; a planned line is not a delivered package.

TSMC’s 2025 disclosure made packaging strategy visible. The operational lesson is to treat CoWoS as a constrained production system with its own capacity and qualification evidence, not as a simple post-processing step after a chip is fabricated.

Editorial analysis: measure finished package flow

For packaging planning, measure the finished-package path rather than only wafer starts. Include available interposers, HBM stacks, substrate supply, assembly cycle time, test yield, thermal assembly, and customer acceptance. A constraint at any stage changes shippable output. This end-to-end view gives capacity discussions a practical denominator that system programs can use. It reveals when added logic wafer starts cannot improve a system delivery date because another package input remains limiting.